1. Field of the Invention
The present invention relates to a semiconductor laser device, in particular, to the semiconductor laser device used for an optical disk system, information processing or as a light source for optical communications.
2. Description of the Related Art
Among the various semiconductor laser devices used for the light source for an optical disk system, a ridge semiconductor laser device is mainly used, and there is a tendency that high-speed response (an improvement in speed of response when an optical output rises in response to injected current) as well as high power output for high-speed writing is demanded. In order to achieve the high-speed response, it is necessary to reduce a value of resistance or a capacitance of the laser device.
For the reduction in value of resistance, on one hand, it is efficient to enlarge the area of a contact layer in the region where current is injected. Therefore, for the conventional ridge semiconductor laser device, a ridge portion is rendered more vertical and an area of a contact layer formed as the top layer of the ridge portion is enlarged, for example, by using anisotropic dry etching for ridge formation. Extending a cavity length is also effective for reducing a value of resistance since the extention increases the contact area.
On the other hand, for the reduction in capacitance, it is effective to reduce a capacitance generated as a result of the p-n junction formed between the block layer and the cladding layer. For example, according to the ridge semiconductor laser device disclosed in Japanese Laid-Open Publications No. H8-222801 and No. 2003-188474, a capacitance reduction layer is inserted between the block layer and the cladding layer.
FIG. 1 is a cross-sectional view showing a structure of the conventional ridge semiconductor laser device described in the Japanese Laid-Open Publications mentioned above.
As shown in FIG. 1, an n-type AlGaInP cladding layer 1102, an active layer 1103, a p-type AlGaInP first cladding layer 1104 and a p-type GaInP etching stop layer 1105 are subsequently laminated on an n-type GaAs substrate 1101, composing the conventional ridge semiconductor laser device.
A ridge portion having a predetermined width is formed by laminating a p-type AlGaInP second cladding layer 1107, a p-type GaInP cap layer 1108 and a p-type GaAs first contact layer 1109 on the p-type GaInP etching stop layer 1105. An n-type AlInP block layer 1110 and a capacitance reduction layer 1106 forming a current/light narrowing structure in a state where the p-type GaAs first contact layer 1109 in the ridge portion is open. It should be noted that the capacitance reduction layer 1106 is made of GaAs or AlInP whose impurity concentration is low.
A p-type GaAs second contact layer 1111 is formed on the n-type AlInP block layer 1110 and the p-type GaAs first contact layer 1109.
In the ridge semiconductor laser device composed as described above, a capacitance reduction layer is inserted between the block layer and the cladding layer. It is therefore possible to reduce the capacitance generated as a result of the p-n junction formed between the block layer and the cladding layer, and reduce the capacitance in the laser device.
Another example of the prior art for realizing the reduction of capacitance is described in Japanese Laid-Open Publication No. 2003-46197 as the ridge semiconductor laser device in which a dielectric layer, not a semiconductor layer forms the current/light narrowing structure so as not to form the problematic p-n junction.
FIG. 2 is a cross-sectional view showing the structure of the conventional ridge semiconductor laser device according to the Japanese Laid-Open Publication No. 2003-46197.
As shown in FIG. 2, in the ridge semiconductor laser device according to the Japanese Laid-Open Publication 2003-46197, an n-type AlGaAs cladding layer 1202, an active layer 1203, a p-type AlGaAs first cladding layer 1204 and a p-type AlGaAs etching stop layer 1205 are sequentially laminated on an n-type GaAs substrate 1201.
A ridge portion which has a predetermined width and is formed in stripes and a wing portion that is convex are formed by laminating a p-type AlGaAs second cladding layer 1206 and a p-type GaAs contact layer 1207 on the p-type AlGaAs etching stop layer 1205. A dielectric layer made up of SiO2, Si3N4 and the like is formed in a state where the p-type GaAs contact layer 1207 is open, so that the current/light narrowing structure is formed.
On the dielectric layer 1208 and the p-type GaAs contact layer 1207, a p-type ohmic electrode 1209 is formed whereas on the n-type GaAs substrate 1201, an n-type ohmic electrode 1210 is formed.
In the ridge semiconductor laser device constructed as above, it is possible to realize the reduction of capacitance since the p-n junction is not formed in the vicinity of the block layer within the device.
However, in the ridge semiconductor laser device according to the Japanese Laid-Open Publications No. H8-222801 and No. 2003-188474, it is not possible to sufficiently reduce the capacitance even with the above solution, since the p-n junction is formed also between the contact layer and the block layer. The problem is that high-speed response cannot be achieved. The semiconductor laser device, in general, has a multi-layered structure formed by crystal growth, which results in the formation of a p-n junction in almost the whole area within the device. This causes another problem in that it is not possible to sufficiently reduce the capacitance even with the above solution, and a high-speed response cannot be realized. In addition, crystal growth is required to be performed three times, which causes a longer lead time and a high price of the chip. The likeliness that a stress at the time of bonding concentrates on the ridge portion when a device is built up using a junction down mounting decreases the reliability of the device.
In the ridge semiconductor laser device according to the Japanese Laid-Open Publication No. 2003-46197, a laser device is manufactured by performing crystal growth one time, the current/light narrowing structure is formed using the dielectric layer, and a wing portion is formed on both sides of the ridge portion. Owing to this, the problems related to high-speed response, lead time, price of a chip and the reliability of the device are respectively resolved. However, another problem is that a refractive index of the practical dielectric layer used for the block layer is small (approximately 2 at minimum) so that there rises a necessity to build a thick cladding layer below the block layer, taking a horizontal angle (Δn: effectual difference in refractive index in and outside the ridge portion) into consideration. This necessity causes an increase in the amount of reactive current, which in turn increases the amount of threshold current. As a result, the temperature characteristic is degraded. Using a dielectric layer which has a thermal conductivity lower than that of a semiconductor layer in order to form the current/light narrowing structure further degrades the temperature characteristic of the device.